Using the NIOS II Processor for HW/SW Codesign of the JPEG2000

JPEG2000 is a recently standardized image compression algorithm that provides significant enhancements over the existing JPEG standard. JPEG2000 differs from widely used compression standards in that it relies on the Discrete Wavelet Transform (DWT) and uses embedded bit plane coding of the wavelet coefficients [1]. Due to the bit-oriented processing techniques used in the standard, full implementation via software is inefficient, making embedded processing slow on standard microprocessors. Possible applications, such as scanners and printers, require a reasonable processing speed, which may be difficult to achieve using existing embedded processors. On the other hand, a full hardware implementation may not utilize the flexibility available in the standard. In order to improve the speed of the JPEG2000 algorithm, while maintaining flexibility, we investigate the use of a co-design approach, using hardware acceleration for the bit oriented and DSP type tasks while leaving packet formation, code-stream formatting and manipulation to software. The NIOS II processor provides an ideal platform for implementing a co-design solution. The customizable ALU allows for the addition of DSP style instructions which will improve the wavelet transform speed and code size. By adding custom peripherals to the system, the bitoriented functions can be moved outside of the software into dedicated hardware. The RTOS (μCos-II) provided with the system allows for parallel processing using multiple custom peripherals. A software implementation of JPEG2000, called Kakadu [2], is used as the implementation framework and baseline for our design. Our proposed design adds the following features to Kakadu: multi-threading with RTOS, custom instructions, and custom peripherals.